Magnetic random access memory (MRAM) that incorporates a magnetic tunnel junction (MTJ) as a memory storage device is a strong candidate to provide a high density, fast (1-30 ns read/write speed), low power, and non-volatile solution for future memory applications. The architecture for MRAM devices is composed of an array of memory cells generally arranged in rows and columns. Each memory cell is comprised of a memory element (MTJ) that is in electrical communication with a transistor through an interconnect stack. The memory elements are programmed by a magnetic field created from pulse current carrying conductors such as copper lines. Typically, two arrays of current carrying conductors that may be called “word lines” and “bit lines” are arranged in a cross point matrix. Normally, the word lines are formed under the MTJs and are isolated from the memory elements by a one or more layers such as an etch stop layer and an interdielectric (ILD) layer. The bit lines contact the top portion of the MTJs and are electrically connected to a conductive cap layer. Additionally, there is a bottom electrode (BE) that contacts the bottom of each MTJ and electrically connects the MTJ with an underlying transistor.
The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin insulating layer such as AlOX that is called a tunnel barrier layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is more or less uniform along a preset direction and is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetization direction can be changed by external magnetic fields. The magnetization direction of the free layer may change in response to external magnetic fields which can be generated by passing currents through a bit line and word line as in a write operation. When the magnetization direction of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the insulating layer (tunnel barrier) than when the magnetization directions of the free and pinned layers are anti-parallel. The MTJ stores digital information (“0” and “1”) as a result of having one of two different magnetic states.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents. Cells which are selectively written to are subject to magnetic fields from both a bit line and word line while adjacent cells (half-selected cells) are only exposed to a bit line or a word line field.
As the MTJ size from a top-down view shrinks relative to the easy axis and hard axis directions (x,y plane), and from a cross-sectional perspective is reduced in thickness (perpendicular to the x,y plane) in order to satisfy higher performance MRAM requirements, the interconnects within the MRAM structure also decrease in size to conform to electrical requirements and space restrictions for high density designs. There is also a greater demand on reliability of the MRAM device since reduced MTJ sizes usually lead to a greater chance of device failure at contact points between adjacent metal layers and tend to cause delamination of the one or more interlayer dielectric (ILD) layers that separate the bit line and word line during CMP processing.
In order to maximize word line and bit line writing efficiency in an MRAM device, one needs to minimize both the distance from the bit line (BIT) to the MTJ free layer and the distance from the word line (WL) to the MTJ free layer. The distance between the WL and MTJ free layer is normally reduced by a cut back in thickness of one or more of the WL, WL ILD, and BE layers. In order to shorten the distance between the BIT and MTJ free layer, one needs to reduce the MTJ capping layer thickness and/or the insulator thickness (if any) between the BIT and MTJ capping layer.
The method of shrinking the distance between the BIT and MTJ free layer depends on the approach taken to create the connection between the BIT and MTJ. In one approach, the BIT directly connects to the MTJ capping layer. This method involves forming a thick hard mask layer normally made of Ta on the MTJ stack of layers. Once the MTJ stack is patterned and etched to form an array of MTJ elements, a layer of insulator material (MTJ ILD) is deposited over the MTJ array. Then CMP is used to remove the MTJ ILD layer until it becomes coplanar with the hard mask surface. Subsequently, the BIT layer is deposited and patterned on the MTJ ILD layer and over the MTJ array. A second approach consists of connecting the BIT to the MTJ through a via. Insulator materials are first deposited after MTJ pattern and etch. Then CMP is employed to planarize the insulator layer but stops before reaching the MTJ hard mask surface. Next, a contact hole layer is photo-patterned and etched to the top surface of the MTJ element. The BIT and via between the BIT and MTJ may be deposited during the same dual damascene process. The second approach is not only costly but has difficulty in controlling distance between the BIT and MTJ from wafer to wafer. The second method is also faced with a serious overlay requirement between the via layer and MTJ array as MTJ size scales down. The first method is more efficient but is limited by CMP dishing and protrusion control capability unless a very thick capping layer about 1000 Angstroms thick or more is used. However, the thick hard mask layer causes a loss in writing efficiency and results in problems for MTJ etch process control. Therefore, a change in mask design for the MTJ layout in an MRAM device is needed to enable the CMP process following MTJ ILD deposition to achieve improved planarization and prevent delamination of dielectric layers above the WL.
A routine search of the prior art revealed the following references. In U.S. Pat. No. 6,928,015, a magnetic memory device is described that has dummy cells in a peripheral portion of the MTJ cell array to achieve uniform pitch throughout the area in center and non-center portions. U.S. Pat. No. 6,916,677 discloses a magnetic memory device having dummy elements in a peripheral circuit portion wherein the sum total of occupying areas of the dummy elements is 5% to 80% of the peripheral circuit portion in order to improve CMP uniformity. U.S. Patent Application 2004/0056289 shows dummy cells that are arranged for uniform CMP speed. U.S. Patent Application 2003/0223283 teaches dummy cells, word lines, and bit lines for uniform trench etching.